N9H20 series is built on the ARM926EJ-S CPU@200MHz, synchronous DRAM, 2D BitBLT accelerator, LCD panel interface, USB 1.1 Host & USB2.0 HS Device core and integrated with JPEG codec, 32-channel SPU (Sound Processing Unit), ADC, DAC, for meeting various kinds of application needs for saving the BOM cost and makes the best choice for LCD application of cost/performance products. Maximum resolution is XVGA (1,024x768)@TFT LCD panel. The 2D BitBLT accelerator accelerates the graphic computation to make the rendering smooth and off-load CPU to save power consumption.
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The open-source code environment provides the product development more flexibility. For reducing
system complexity while cutting the BOM cost, the N9H20 series provides MCP (Multi-Chip Package)
to ensure higher performance and to minimize the system design efforts. Total BOM cost could be cut
by employing 2-layer PCB along with the elimination of external parts, EMI prevention components and saving board design space.
Nuvoton NK-N9H20 Features: -
CPU:
- ARM926EJ-S 32-bit RISC CPU with 8KB I-Cache &8KB D-Cache
- Frequency up [email protected] core power operation voltage
- JTAG interface supported for development and debugging
Internal SRAM & ROM:
- 8KB internal SRAM and 16KB IBR internal booting ROM supported
- IBR booting messages displayed by UART console for debugging supported
Different system booting modes supported:
- Memory card
- SD card or eMMC Flash device
- SD-to-NAND flash bridge
- Raw NAND Flash
- SPI Flash
- USB
UART:
A high speed UART supported: -
- Baud rate is up to 1M bps
- 4 signals TX, RX, CTS and RTS supported
A normal UART supported:
- Baud rate is up to 115.2K bps
- 2 signals TX and RX supported only
SPI:
Two SPI controller is supported: -
- Both master and slave mode are supported in SPI interface
- Two chip selection signals for two SPI devices
I2C:
- One I2C channel supported
- Compatible with Philips’s I2C standard and only master mode supported
- Multi-master operation supported
To know more Nuvoton NK-N9H20 – datasheet